This invention pertains to microlithography (projection-transfer) of a pattern, defined by a reticle, to a sensitive substrate using a charged particle beam as an energy beam. Microlithography is used generally in the fabrication of semiconductor integrated circuits and displays. More specifically, the invention pertains to microlithography methods in which adverse effects of errors of pattern overlayer and subfield stitching are reduced.
Charged-particle-beam (CPB) microlithography is a promising method for used in fabrication of semiconductor integrated circuits, displays, and other devices demanding the accurate transfer of extremely fine patterns (having linewidths of 0.1 xcexcm or less).
Much current development effort is aimed at producing a practical CPB microlithography apparatus that can achieve desired transfer accuracy at an acceptable throughput. One current impediment to achieving acceptable throughput is that the pattern for an entire semiconductor device (xe2x80x9cchipxe2x80x9d) cannot be projection-transferred at one time using CPB microlithography. This is because, inter alia, producing a CPB optical system having an optical field sufficiently large to image an entire chip-layer pattern has not been accomplished. Hence, the pattern, as defined on a reticle, is divided or segmented into pattern portions usually termed xe2x80x9csubfieldsxe2x80x9d that are individually exposed according to a pre-established order.
The projected images of the subfields on the wafer (or other suitable sensitive substrate) desirably are situated contiguously with respect to each other so that the images are xe2x80x9cstitchedxe2x80x9d together in a manner that forms the entire pattern on the wafer. A reticle for this type of pattern transfer is termed a xe2x80x9cdividedxe2x80x9d or xe2x80x9csegmentedxe2x80x9d reticle, and microlithography performed using such a reticle is termed xe2x80x9cdivided-reticlexe2x80x9d microlithography.
In a segmented reticle, each subfield is dimensioned to fit within the optical field of the CPB optical system. Progression of exposure from one subfield to the next can occur either by scanning the charged particle beam in a continuous manner or by stepwise motion of the respective stages on which the reticle and wafer are mounted.
According to a conventional approach, the reticle is divided into subfields all identically sized and each having a square or rectangular profile. When dividing a pattern in this manner, it is inevitable that subfield boundaries will extend across conductor lines and other pattern features. When projected onto the wafer, such conductor lines and the like must be imaged such that intact connections of conductors are established properly between adjacent subfields (i.e., the subfields are properly xe2x80x9cstitchedxe2x80x9d together on the wafer). As a first example, if the projected images of adjacent subfields containing an interconnecting conductor are not located properly on the wafer, then a break or short can be formed in the conductor as imaged on the wafer. As a second example, if a pattern element extending between a source and a gate of a transistor or between a gate and a drain of a transistor of a semiconductor device crosses a subfield boundary, and if a subfield-stitching defect occurs at that intersection, then the yield of fully functional semiconductor devices is compromised. The incidence frequency of xe2x80x9csubfield-stitchingxe2x80x9d defects (i.e., defects in the manner in which pattern elements extending across subfield boundaries are connected together between adjacent subfields as projected) increases with an increase in the number of locations on the wafer where subfield boundaries and pattern features intersect. As semiconductor devices (e.g., microprocessors and memories) become increasingly complex and miniaturized, subfield-stitching and layer-registration defects experienced during fabrication steps involving CPB microlithography tend to increase. This results in substantial loss of production efficiency and loss of salable product through rejects.
Interconnection defects as summarized above can occur in a single layer of a semiconductor device; single-layer errors generally are termed xe2x80x9csubfield-stitchingxe2x80x9d errors as noted above. Similar errors can also occur between layers as formed on the wafer, and multi-layer errors generally are termed xe2x80x9coverlayerxe2x80x9d errors or xe2x80x9cpattern-registrationxe2x80x9d errors.
Therefore, there is a need for CPB microlithography methods exhibiting a significantly reduced incidence of subfield-stitching and overlayer defects in the patterns as projected onto a wafer.
In view of the shortcomings of the prior art as summarized above, an object of the invention is to provide CPB microlithography methods in which defects arising from subfield-stitching errors and/or overlayer errors are reduced.
According to a first aspect of the invention, methods are provided in which a pattern, to be transferred to a sensitive substrate (xe2x80x9cwaferxe2x80x9d) by CPB microlithography, is divided on the reticle into multiple subfields. As the subfields are projection-transferred onto the wafer, the projected subfields are positioned so as to stitch together the subfield images in a way that forms the entire pattern. On the reticle, subfield boundaries are established apart from regions and areas of the pattern where stitching accuracy of the projected pattern must be relatively high compared to other regions and areas of the pattern. For example, a source or drain of a transistor is normally defined in a diffusion layer. A gate electrode, defined in a subsequently applied layer, must be applied with very high positional accuracy to the diffusion layer. A subfield boundary is not provided in such a region.
According to another embodiment of methods according to the invention, if a subfield boundary must cross a pattern element, such crossing of the element by the boundary is made where the element has an internal angle of 225 degrees or greater. By making the intersection in such a region, the probability of a break occurring in the pattern element (as projected onto the wafer) is low in the event of a subfield-stitching error or dislocation in the respective subfields as projected. I.e., at a region of a pattern element characterized by such a large internal angle, proximity effects tend to compensate for situations that otherwise would have a higher probability of causing a break in the element crossing the boundary. The internal angle desirably is at least 225 degrees so as to adequately distinguish from the very common internal angle of 180 degrees.
According to yet another embodiment, the subfield boundaries of each layer are at different relative locations, established independently in each layer. Hence, it is possible to make the subfield (and pattern feature) connections in each pattern layer inconspicuous.